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disturbed zero output signsl
释义
disturbed zero output signsl
受扰“0”输出信号
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cycle stealing
cycle stealing basis
cycle steal mode
cycle stilling base
cycle structure
cycle testing
cycle time
cycle trace algorithm
cycle vector
cyclic
cyclic access
cyclic A/D converter
cyclical
operator interrupt
operator intervention
operator L and R
operator language
operator monitor
operator-monitor communication
operator notation
operator part
operator precedence grammar
operator-precedence method
operator priority order language
operator register
Macos计算机英汉词典包含84405条计算机术语英汉翻译词条,基本涵盖了全部常用计算机术语的翻译及用法,是计算机学习及翻译工作的有利工具。
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更新时间:2024/11/11 8:20:26